View GS881Z36T-100I_3337190.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev: 1.10 8/2000 1/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. nobl is a trademark of cypress semiconductor corp.. ntram is a trademark of samsung electronics co.. zbt is a trademark of integ rated device technology, inc. preliminary gs 881z 18/36 t -1 1 /100 /80/66 8 mb pipelined and flow through synchronous nbt sram s 100 m h z ?66 mhz 3.3 v v dd 2.5 v and 3.3 v v ddq 100-pin tqfp commercial temp industrial temp features ? 512 k x 18 and 256 k x 36 configurations ? user - configurable pipelined and flow through mode ? nbt (no bus turn around) functionality allows zero wait ? read-write-read bus utilization ? fully pin - compatible with both pipelined and flow through ntram?, nobl? and zbt? srams ? ieee 1149.1 jtag-compatible boundary scan ? on-chip write parity checking; even or odd selectable ? pin-compatible with 2m, 4 m and 16m devices ? 3.3 v +10%/?5% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleave burst mode ? byte write operation (9 - bit bytes) ? 3 chip enable signals for easy depth expansion ? clock control, registered, address, data, and control ? zz pin for automatic power-down ? jedec-standard 100-lead tqfp package functional description the gs 881z 18/36 t is a n 8m bit synchronous static sram. gsi's nbt srams, like zbt, ntram, nobl or other pipelined read/double late write or flow through read/single late write srams, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. burst order control ( lbo ) must be tied to a power rail for proper operation. asynchronous inputs include the sleep mode enable ( zz ) and output enable. output enable can be used to override the synchronous control of the output drivers and turn the ram's output drivers off at any time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation required by asynchronous srams and simplifies input signal timing. the gs 881z 18/36 t may be configured by the user to operate in pipeline or flow through mode. operating as a pipelined synchronous device, in addition to the rising - edge - triggered registers that capture input signals, the device incorporates a rising - edge -triggered output register. for read cycles, pipelined sram output data is temporarily stored by the edge -t riggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. the gs 881z 18/36 t is implemented with gsi's high performance cmos technology and is available in a jedec- standard 100-pin tqfp package. -11 -100 - 80 - 66 pipeline 3-1-1-1 t cycle t kq i dd 10 ns 4.5 ns 210 ma 10 ns 4.5 ns 210 ma 12.5 ns 4. 8 ns 190 ma 15 ns 5 ns 170 ma flow through 2-1-1-1 t kq t cycle i dd 11 ns 15 ns 150 ma 12 ns 15 ns 150 ma 14 ns 15 ns 130 ma 18 ns 20 ns 130 ma a b c d e f r w r w r w q a d b q c d d q e q a d b q c d d q e clock address read/write flow through data i/o pipelined data i/o flow through and pipelined nbt sram back-to-back read/write cycles
rev: 1.10 8/2000 2/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 gs881z18t pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b1 dq b2 v ss v ddq dq b3 dq b4 ft v dd dp v ss dq b5 dq b6 v ddq v ss dq b7 dq b8 dq b9 v ss v ddq v ddq v ss dq a8 dq a7 v ss v ddq dq a6 dq a5 v ss qe v dd zz dq a4 dq a3 v ddq v ss dq a2 dq a1 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 t m s t d i v s s v d d t d o t c k a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 n c n c b b b a e 3 c k w c k e v d d v s s g a d v n c a 1 7 a 8 a 9 a 1 5 512k x 18 top view dq a9 a 18 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
rev: 1.10 8/2000 3/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 gs881z36t pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 ft v dd dp v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss qe v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 t m s t d i v s s v d d t d o t c k a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 b d b c b b b a e 3 c k w c k e v d d v s s g a d v n c a 1 7 a 8 a 9 a 1 5 256k x 36 top view dq b5 dq b9 dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 dq a9 dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 dq d9 dq c5 dq c9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
rev: 1.10 8/2000 4/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 100-pin tqfp pin descriptions pin location symbol type description 37, 36 a 0 , a 1 in burst address inputs?preload the burst counter 35, 34, 33, 32, 100, 99, 83, 82, 81, 50, 49, 48, 47, 46, 45, 44 a 2 ?a 17 in address inputs 80 a 18 in address input (x18 version only) 89 ck in clock input signal 93 b a in byte write signal for data inputs dq a1 ?dq a9 ; active low 94 b b in byte write signal for data inputs dq b1 ?dq b9 ; active low 95 b c in byte write signal for data inputs dq c1 ?dq c9 ; active low (x36 version only) 96 b d in byte write signal for data inputs dq d1 ?dq d9 ; active low (x36 version only) 88 w in write enable; active low 98 e 1 in chip enable; active low 97 e 2 in chip enable; active high; for self decoded depth expansion 92 e 3 in chip enable; active low; for self decoded depth expansion 86 g in output enable; active low 85 adv in advance/ load ?burst address counter control pin 87 cke in clock input buffer enable; active low 58, 59, 62,63, 68, 69, 72, 73, 74 dq a1 ?dq a9 i/o byte a data input and output pins (x18 version only) 8, 9, 12, 13, 18, 19, 22, 23, 24 dq b1 ?dq b9 i/o byte b data input and output pins (x18 version only) 51, 52, 53, 56, 57, 75, 78, 79, 1, 2, 3, 6, 7, 25, 28, 29, 30 nc ? no connect (x18 version only) 51, 52, 53, 56, 57, 58, 59, 62,63 dq a1 ?dq a9 i/o byte a data input and output pins (x36 versions only) 68, 69, 72, 73, 74, 75, 78, 79, 80 dq b1 ?dq b9 i/o byte b data input and output pins (x36 versions only) 1, 2, 3, 6, 7, 8, 9, 12, 13 dq c1 ?dq c9 i/o byte c data input and output pins (x36 versions only) 18, 19, 22, 23, 24, 25, 28, 29, 30 dq d1 ?dq d9 i/o byte d data input and output pins (x36 versions only) 64 zz in power down control; active high 14 ft in pipeline/flow through mode control; active low 31 lbo in linear burst order; active low
rev: 1.10 8/2000 5/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 38 tms ? scan test mode select 39 tdi ? scan test data in 42 tdo ? scan test data out 43 tck ? scan test clock 15, 41, 65, 91 v dd in 3.3 v power supply 5,10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss in ground 4, 11, 20, 27, 54, 61, 70, 77 v ddq in 3.3 v output power supply for noise reduction 16 dp in parity input?1 = even, 0 = odd 66 qe out parity error out?open drain output 42, 43,, 84 nc ? no connect pin location symbol type description
rev: 1.10 8/2000 6/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 gs 881z 18/36 bytesafe nbt sram functional block diagram k 1 8 s a 1 s a 0 b u r s t c o u n t e r l b o a d v m e m o r y a r r a y g c k c k e d q f t q e d p d q a ? d q n k s a 1 ? s a 0 ? d q m a t c h w r i t e a d d r e s s r e g i s t e r 2 w r i t e a d d r e s s r e g i s t e r 1 w r i t e d a t a r e g i s t e r 2 w r i t e d a t a r e g i s t e r 1 k k k k k k s e n s e a m p s w r i t e d r i v e r s r e a d , w r i t e a n d d a t a c o h e r e n c y c o n t r o l l o g i c d q k p a r i t y c h e c k f t a 0 ? a n e 3 e 2 e 1 w b d b c b b b a
rev: 1.10 8/2000 7/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 functional details clocking deassertion of the clock enable ( cke ) input blocks the clock input from reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observe clock enable set-up or hold requirements will result in erratic operation. pipeline mode read and write operations all inputs (with the exception of output enable, linear burst order and sleep) are synchronized to rising clock edges. single cy cle read and write operations must be initiated with the advance/ load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting all three of the chip enable inputs ( e 1 , e 2 , and e 3 ). deassertion of any one of the enable inputs will deactivate the device. read operation is initiated when the following conditions are satisfied at the rising edge of clock: cke is asserted low, all three chip enables ( e1 , e2 , and e3 ) are active, the write enable input signals w is deasserted high, and adv is asserted low. the address presented to the address inputs is latched in to address register and presented to the memory core and control logic. the contro l logic determines that a read access is in progress and allows the requested data to propagate to the input of the output registe r. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operation occurs when the ram is selected, cke is active and the write input is sampled low at the rising edge of clock. the byte write enable inputs ( b a , b b , b c, and b d ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. the pipelined nbt sram provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). at the first rising edge of clock, enable, write, byte write(s) , and address are registered. the data in associated with that address is required at the third rising edge of clock. flow through mode read and write operations operation of the ram in flow through mode is very similar to operations in pipeline mode. activation of a read cycle and the use of the burst address counter is identical. in flow through mode the device may begin driving out new data immediately after new address are clocked into the ram, rather than holding new data until the following (second) clock edge. therefore , in flow through mode the read pipeline is one cycle shorter than in pipeline mode. write operations are initiated in the same way as well , but differ in that the write pipeline is one cycle shorter, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. while the pipelined nbt rams implement a double late write protocol, in flow through mode a single late write protocol mode is observed. therefore, in flow through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. function w b a b b b c b d read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h
rev: 1.10 8/2000 8/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 synchronous truth table operation type address e 1 e 2 e 3 zz adv w bx g cke ck dq notes deselect cycle, power down d none h x x l l x x x l l-h high-z deselect cycle, power down d none x x h l l x x x l l-h high-z deselect cycle, power down d none x l x l l x x x l l-h high-z deselect cycle, continue d none x x x l h x x x l l-h high-z 1 read cycle, begin burst r external l h l l l h x l l l-h q read cycle, continue burst b next x x x l h x x l l l-h q 1,10 nop/read, begin burst r external l h l l l h x h l l-h high-z 2 dummy read, continue burst b next x x x l h x x h l l-h high-z 1,2,10 write cycle, begin burst w external l h l l l l l x l l-h d 3 write cycle, continue burst b next x x x l h x l x l l-h d 1,3,10 nop/write abort, begin burst w none l h l l l l h x l l-h high-z 2,3 write abort, continue burst b next x x x l h x h x l l-h high-z 1,2,3,10 clock edge ignore, stall current x x x l x x x x h l-h - 4 sleep mode none x x x h x x x x x x high-z notes: 1. continue burst cycles, whether read or write, use the same control inputs; a deselect continue cycle can only be entered into if a deselect cycle is executed first 2. dummy read and write abort can be considered nops because the sram performs no operation. a write abort occurs when the w pin is sampled low but no byte write pins are active, so no write operation is performed. 3. g can be wired low to minimize the number of control signals provided to the sram. output drivers will automatically turn off dur ing write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensures all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminated for all burst continue cycles.
rev: 1.10 8/2000 9/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 deselect new read new write burst read burst write w r b r b w d d b b w r d b w r d d pipeline and flow through read - write control state diagram current state (n) next state (n+1) transition ? input command code key notes 1. the hold command ( cke low) is not shown because it prevents any state change. 2. w, r, b and d represent input command codes , as indicated in the synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ? ? ? current state and next state definition for pipelined and flow through read/write control state diagram w r
rev: 1.10 8/2000 10/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 intermediate intermediate intermediate intermediate intermediate intermediate high z (data in) data out (q valid) high z b w b r b d r w r w d d pipeline mode data i/o state diagram current state (n) next state (n+2) transition ? input command code key transition intermediate state (n+1) notes 1. the hold command ( cke low) is not shown because it prevents any state change. 2. w, r, b , and d represent input command codes as indicated in the truth tables. clock (ck) command current state intermediate ? n n+1 n+2 n+3 ? ? ? current state and next state definition for pipeline mode data i/o state diagram next state state
rev: 1.10 8/2000 11/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command ( cke low) is not shown because it prevents any state change. 2. w, r, b , and d represent input command codes as indicated in the truth tables. flow through mode data i/o state diagram clock (ck) command current state next state ? n n+1 n+2 n+3 ? ? ? current state and next state definition for: pipeline and flow through read write control state diagram
rev: 1.10 8/2000 12/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 burst cycles although nbt rams are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. nbt srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the counter generated address to read or write the sram. the starting address for the first cycle in a burst cycle series is loaded into the sram by driving the adv pin low, i nto load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the linear burst order pin ( lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pin tied high, interleaved burst sequence is selected. see the tabl es below for details. note: there are pull-up device s on the lbo , dp and ft pin s and a pull down device on the zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. burst counter sequences bpr 1999.05.18 sleep mode during normal operation, zz must be pulled low, either by the user or by its internal pull down resistor. when zz is pulled high , the sram will enter a power sleep mode after 2 cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram operates normally after 2 cycles of wake up time. mode pin functions mode name pin name state function burst order control lbo l linear burst h or nc interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb bytesafe data parity control dp l check for odd parity h or nc check for even parity linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.10 8/2000 13/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an asynchronous, active high input that causes the device to enter sleep mod e. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiate d until valid pending operations are completed. similarly, when exiting sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram designing for compatibility the gsi nbt srams offer users a configurable selection between flow through mode and pipeline mode via the ft signal found on pin 14 . not all vendors offer this option, however most mark pin 14 as v dd or v ddq on pipelined parts and v ss on flow through parts. gsi nbt srams are fully compatible with these sockets. pin 66, a no connect (nc) on gsi?s gs 880z 18/36 nbt sram, the parity error open drain output on gsi?s gs 881z 18/36 nbt sram, is often marked as a power pin on other vendor?s nbt-compatible srams. specifically, it is marked v dd or v ddq on pipelined parts and v ss on flow through parts. users of gsi nbt devices who are not actually using the bytesafe? parity feature may want to design the board site for the ram with pin 66 tied high through a 1k ohm resistor in pipeline mode applications or tied low in flow through mode applications in order to keep the option to use non-configurable devices open. by using the pull-u p resistor, rather than tying the pin to one of the power rails, users interested in upgrading to gsi?s bytesafe nbt srams (gs 881z 18/36), featuring parity error detection and jtag boundary scan, will be ready for connection to the active low, open drain parity error output driver at pin 66 on gsi?s tqfp bytesafe rams. bytesafe ? parity functions this sram includes a write data parity check that checks the validity of data coming into the ram on write cycles. in flow through mode, write data errors are reported in the cycle following the data input cycle. in pipeline mode, write data errors ar e reported one clock cycle later. (see write parity error output timing diagram .) the data parity mode (dp) pin must be tied high to set the ram to check for even parity or low to check for odd parity. read data parity is not checked by the ram as data. validity is best established at the data?s destination. the parity error output is an open drain output and drives low to indica te a parity error. multiple parity error output pins may share a common pull-up resistor. ck zz tzzr tzzh tzzs ~ ~ ~ ~ sleep
rev: 1.10 8/2000 14/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 write parity error output timing diagram bpr 1999.05.18 ck d in a d in b d in c d in d d in e tkq tlz dq qe f l o w t h r o u g h m o d e p i p e l i n e d m o d e tkq tlz dq qe d in a d in b d in c d in d d in e err a err a err c err c thz tkqx thz tkqx
rev: 1.10 8/2000 15/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomme nded operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an extended period of time, may affect reliability of this component. notes: 1. unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 v v ddq 2.375 v (i.e., 2.5 v i/o) and 3.6 v v ddq 3.135 v (i.e., 3.3 v i/o), and quoted at whichever condition is worst case. 2. this device features input buffers compatible with both 3.3 v and 2.5 v i/o drivers. 3. most speed grades and configurations of this device are of f ered in both commercial and industrial temperature ranges. the part number of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. input under/overshoot voltage must be ?2 v > vi < v dd +2 v with a pulse width not to exceed 20% tkc. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 4.6 v v ddq voltage in v ddq pins ?0.5 to v dd v v ck voltage on clock input pin ?0.5 to 6 v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ?0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/?20 ma i out output current on any i/o pin +/?20 ma p d package power dissipation 1.5 w t stg storage temperature ?55 to 125 o c t bias temperature under bias ?55 to 125 o c recommended operating conditions parameter symbol min. typ. max. unit notes supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 2.375 2.5 v dd v 1 input high voltage v ih 1.7 ? v dd +0.3 v 2 input low voltage v il ?0.3 ? 0.8 v 2 ambient temperature (commercial range versions) t a 0 25 70 c 3 ambient temperature (industrial range versions) t a ?40 25 85 c 3
rev: 1.10 8/2000 16/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 note: these parameters are sample tested. notes: 1. junction temperature is a function of sram power dissipation, package thermal resistance, mounting board temperature, ambient. t emper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1 capacitance (t a = 25 o c , f = 1 mh z , v dd = 3.3 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf input/output capacitance c i/o v out = 0 v 6 7 pf package thermal characteristics rating layer board symbol max unit notes junction to ambient (at 200 lfm) single r q ja 40 c/w 1,2 junction to ambient (at 200 lfm) four r q ja 24 c/w 1,2 junction to case (top) ? r q jc 9 c/w 3 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 1.10 8/2000 17/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz 4. device is deselected as defined by the truth table. ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ?1 ua 1 ua zz input current i in zz v dd 3 v in 3 v ih 0 v v in v ih ?1 ua ?1 ua 1 ua 300 ua mode pin input current i in m v dd 3 v in 3 v il 0 v v in v il ?300 ua ?1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v dq vt = 1.25 v 50 w 30pf * dq 2.5 v output load 1 output load 2 225 w 225 w 5pf * * distributed test jig capacitance
rev: 1.10 8/2000 18/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 operating currents parameter test conditions symbol -11 -100 -80 -66 unit 0 to 70c -40 to +85c 0 to 70c -40 to +85c 0 to 70c -40 to +85c 0 to 70c -40 to +85c operating current device selected; all other inputs 3 v ih or v il output open i dd pipeline 210 220 210 220 190 200 170 180 ma i dd flow-through 150 160 150 160 130 140 130 140 ma standby current zz 3 v dd ? 0.2 v i sb pipeline 30 40 30 40 30 40 30 40 ma i sb flow-through 30 40 30 40 30 40 30 40 ma deselect current device deselected; all other inputs 3 v ih or v il i dd pipeline 80 90 80 90 70 80 65 75 ma i dd flow-through 65 75 65 75 55 65 55 65 ma
rev: 1.10 8/2000 19/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 ac electrical characteristics parameter symbol -11 -100 -80 -66 unit min max min max min max min max pipeline clock cycle time tkc 10 ? 10 ? 12 .5 ? 1 5 ? ns clock to output valid tkq ? 4.5 ? 4.5 ? 4. 8 ? 5 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow- through clock cycle time tkc 15.0 ? 15.0 ? 15.0 ? 20 ? ns clock to output valid tkq ? 11.0 ? 12.0 ? 1 4 .0 ? 1 8 .0 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.7 ? 2 ? 2 ? 2 .3 ? ns clock low time tkl 2 ? 2.2 ? 2 .2 ? 2. 5 ? ns clock to output in high-z thz 1 1.5 4.0 1.5 4.5 1.5 4. 8 1.5 5 ns g to output valid toe ? 4.0 ? 4.5 ? 4. 8 ? 5 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 4.0 ? 4.5 ? 4. 8 ? 5 ns setup time ts 1.5 ? 2.0 ? ? 2.0 ? 2.0 ns hold time th 0.5 ? 0.5 ? ? 0.5 ? 0.5 ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns notes: 1. these parameters are sampled and are not 100% tested . 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycle, zz must meet the specified setup and hold times as specified above.
rev: 1.10 8/2000 20/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 pipeline mode read/write cycle timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 th ts th ck cke e * adv tkh w tkl tkc ts b n a 0 ?an a1 th ts a2 a3 d(a1) d(a2) q(a3) q q(a6) th ts d d(a5) tkqlz tkq tkqhz toehz toelz tkqx tkhqz tglqv g 1 2 3 4 5 6 7 8 9 10 command write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect don?t care undefined dq a ?dq d th ts th ts th ts a4 a5 a6 a7 q(a4) (a4+1) (a2+1)
rev: 1.10 8/2000 21/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 pipeline mode no-op, stall and deselect timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv w bn a 0 ? an a1 a5 d(a1) q(a2) q(a3) q(a5) dq 1 2 3 4 5 6 7 8 9 10 command write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) continue don?t care undefined d(a4) tkhqz tkqhz deselect deselect th ts a2 a3 a4 th ts th ts th ts
rev: 1.10 8/2000 22/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 flow through mode read/write cycle timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv tkh w tkl tkc b n a 0 ?an th ts a7 dq 1 2 3 4 5 6 7 8 9 10 command write d(a1) write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect don?t care undefined th ts th ts th ts th ts th ts a1 a2 a3 a4 a5 a6 d(a1) d(a2) q(a3) q q(a6) th ts d d(a5) tkqlz tkq tkqhz toehz toelz tkqx tkhqz tglqv q(a4) (a4+1) (a2+1) g
rev: 1.10 8/2000 23/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 flow through mode no-op, stall and deselect timing *note: e = high (false) if e 1 = 1 or e 2 = 0 or e 3 = 1 ck cke e * adv w bn a 0 ? an q(a5) dq 1 2 3 4 5 6 7 8 9 10 command write d(a1) read q(a2) stall read q(a3) write d(a4) stall nop read q(a5) continue don?t care undefined d(a4) tkhqz tkqhz deselect deselect d(a1) q(a2) q(a3) a1 a5 a2 a3 a4 th ts th ts th ts
rev: 1.10 8/2000 24/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 jtag port operation overview the jtag port on this ram operates in a manner consistent with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag), but does not implement all of the functions required for 1149.1 compliance. some functions have been modified or eliminated because they can slow the ram. nevertheless, the ram supports 1149.1-1990 tap (test access port) controller architecture, and can be expected to function in a manner that does not conflict with the operatio n of standard 1149.1 compliant devices. the jtag port interfaces with conventional ttl / cmos logic level signaling. disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unless clocked. tck, tdi, and tms are designed with internal pull-up circuits. to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag port registers overview the various jtag registers, refered to as tap registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on the next falling edge of tck. when a register is selected it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run, test/idle or the various data register states. instructions are 3 bits long. the instruction register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single-bit register that can be placed between tdi and tdo. it allows serial test data to be passed thr ough the rams jtag port to another device in the scan chain with as little delay as possible. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while t ms is held high for five rising edges of tck. the tap controller is also reset automaticly at power-up.
rev: 1.10 8/2000 25/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 boundary scan register boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boun dary scan register also includes a number of place holder flip flops (always set to a logic 1). the relationship between the device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and t hen is placed between the tdi and tdo pins when the controller is moved to shift-dr state. two tap instructions can be used to activate the boundary scan register. jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device specif ic id register contents die revision code not used i/o configuration gsi technology jedec vendor id code p r e s e n c e r e g i s t e r bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 x18 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.10 8/2000 26/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 (private) instructions. some public instructions, are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the 1149.1 conventions, it is not 1194.1- compliant because some of the mandatory instructions are not fully implemented. the tap on this device may be used to monitor all input and i/o pads, but cannot be used to load address, data or control signals into the ram or to preload the i/o buffers.t his device will not perform extest, intest or the sample/preload command. when the tap controller is placed in capture-ir state the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shift-ir state the instruction register is placed between tdi and tdo. in this state the des ired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing o f other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample/preload instruction is loaded in the instruc- tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bou ndary scan select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1
rev: 1.10 8/2000 27/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 register. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring con- tents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inp uts will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input d ata cap- ture set-up plus hold time (tts plus tth ). the rams clock inputs need not be paused for any other tap operation except capturin g the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register be tween the tdi and tdo pins. because the preload portion of the command is not implemented in this device, moving the controller to the upd ate- dr state with the sample / preload instruction loaded in the instruction register has the same effect as the pause-dr command. t his functionality is not standard 1149.1-compliant. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length i t may be in the device, is loaded with all logic 0s. extest is not implemented in this device. therefore, this device is not 1149.1-complian t. neverthe- less, this ram?s tap does respond to an all zeros instruction, as follows. with the extest (000) instruction loaded in the instr uction regis- ter the ram responds just as it does in response to the bypass instruction described above. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (high-z ) and the bound- ary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 replicates bypass instruction. places bypass register between tdi and tdo. this ram does not implement 1149.1 extest function. *not 1149.1 compliant * 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. this ram does not implement 1149.1 preload function. *not 1149.1 compliant * 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
rev: 1.10 8/2000 28/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input high voltage v iht 1.7 v dd +0.3 v 1, 2 test port input low voltage v ilt ?0.3 0.8 v 1, 2 tms, tck and tdi input leakage current i in th ?300 1 ua 3 tms, tck and tdi input leakage current i in tl ?1 1 ua 4 tdo output leakage current i olt ?1 1 ua 5 test port output high voltage v oht 2.4 ? v 6, 7 test port output low voltage v olt ? 0.4 v 6, 8 notes: 1. this device features input buffers compatible with both 3.3 v and 2.5 v i/o drivers. 2. input under/overshoot voltage must be ?2 v > vi < v dd +2 v with a pulse width not to exceed 20% ttkc. 3. v dd 3 v in 3 v il 4. 0 v v in v il 5. output disable, v out = 0 to v dd 6. the tdo output driver is served by the v dd supply. 7. i oh = ?4 ma 8. i ol = +4 ma notes: 1. include scope and jig capacitance. jtag port ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v dq v t = 1.25 v 50 w 30pf * jtag port ac test load * distributed test jig capacitance
rev: 1.10 8/2000 29/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 jtag port timing diagram jtag port ac electrical characteristics parameter symbol min max unit tck cycle time ttkc 20 ? ns tck low to tdo valid ttkq ? 10 ns tck high pulse width ttkh 10 ? ns tck low pulse width ttkl 10 ? ns tdi & tms set up time tts 5 ? ns tdi & tms hold time tth 5 ? ns ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc
rev: 1.10 8/2000 30/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 gs 881z 18/36t tqfp boundary scan register notes: 1. the boundary scan register contains a number of registers that are not connected to any pin. they default to the value shown at reset. 2. registers are listed in exit order (i.e., location 1 is the first out of the tdo pin). 3. nc = no connect, na = not active, ph = place holder (no associated pin) order x36 x18 pin 1 ph = 0 n/a 2 ph = 0 n/a 3 a 10 44 4 a 11 45 5 a 12 46 6 a 13 47 7 a 14 48 8 a 15 49 9 a 16 50 10 x36 = dq a9 nc = 1 51 11 dq a8 nc = 1 52 12 dq a7 nc = 1 53 13 dq a6 nc = 1 56 14 dq a5 nc = 1 57 15 dq a4 dq a1 58 16 dq a3 dq a2 59 17 dq a2 dq a3 62 18 dq a1 dq a4 63 19 zz 64 20 qe 66 21 dq b1 dq a5 68 22 dq b2 dq a6 69 23 dq b3 dq a7 72 24 dq b4 dq a8 73 25 dq b5 dq a9 74 26 dq b6 nc = 1 75 27 dq b7 nc = 1 78 28 dq b8 nc = 1 79 29 x36 = dq b9 a 18 80 30 a 9 81 31 a 8 82 32 a 17 83 33 nc = 0 84 34 adv 85 35 g 86 36 cke 87 37 w 88 38 ck 89 39 ph = 1 n/a 40 ph = 1 n/a 41 e 3 92 42 b a 93 43 b b 94 44 b c nc = 1 95 45 b d nc = 1 96 46 e 2 97 47 e 1 98 48 a 7 99 49 a 6 100 50 x36 = dq c9 nc = 1 1 51 dq c8 nc = 1 2 52 dq c7 nc = 1 3 53 dq c6 nc = 1 6 54 dq c5 nc = 1 7 55 dq c4 dq b1 8 56 dq c3 dq b2 9 57 dq c2 dq b3 12 58 dq c1 dq b4 13 order x36 x18 pin 59 ft 14 60 dp 16 61 ph = 1 n/a 62 dq d1 dq b5 18 63 dq d2 dq b6 19 64 dq d3 dq b7 22 65 dq d4 dq b8 23 66 dq d5 dq b9 24 67 dq d6 nc = 1 25 68 dq d7 nc = 1 28 69 dq d8 nc = 1 29 70 x36 = dq d9 nc = 1 30 71 lbo 31 72 a 5 32 73 a 4 33 74 a 3 34 75 a 2 35 76 a 1 36 77 a 0 37 78 ph = 0 n/a bpr 1999.08.11 order x36 x18 pin
rev: 1.10 8/2000 31/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 output driver characteristics bpr 1999.05.18 -140.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 v out (pull down) vddq - v out (pull up) i out (ma) 3.6v pd hd 3.3v pd hd 3.1v pd hd 3.1v pu hd 3.3v pu hd 3.6v pu hd pull up drivers pull down drivers vddq vout i out vss
rev: 1.10 8/2000 32/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 tqfp package drawing bpr 1999.05.18 d 1 d e1 e p i n 1 b e c l l1 a2 a1 y q notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity ? ? 0.10 q lead angle 0 ? 7
rev: 1.10 8/2000 33/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 ordering information?gsi nbt synchronous sram org part number 1 type package speed 2 (mhz/ns) t a 3 status 512k x 18 gs881z18t-11 bytesafe nbt pipeline/flow through tqfp 100/11 c 512k x 18 gs881z18t-100 bytesafe nbt pipeline/flow through tqfp 100/12 c 512k x 18 gs881z18t-80 bytesafe nbt pipeline/flow through tqfp 80/14 c 512k x 18 gs881z18t-66 bytesafe nbt pipeline/flow through tqfp 66/18 c 256k x 36 gs881z36t-11 bytesafe nbt pipeline/flow through tqfp 100/11 c 256k x 36 gs881z36t-100 bytesafe nbt pipeline/flow through tqfp 100/12 c 256k x 36 gs881z36t-80 bytesafe nbt pipeline/flow through tqfp 80/14 c 256k x 36 gs881z36t-66 bytesafe nbt pipeline/flow through tqfp 66/18 c 512k x 18 gs881z18t-11i bytesafe nbt pipeline/flow through tqfp 100/11 i 512k x 18 gs881z18t-100i bytesafe nbt pipeline/flow through tqfp 100/12 i 512k x 18 gs881z18t-80i bytesafe nbt pipeline/flow through tqfp 80/14 i 512k x 18 gs881z18t-66i bytesafe nbt pipeline/flow through tqfp 66/18 i 256k x 36 gs881z36t-11i bytesafe nbt pipeline/flow through tqfp 100/11 i 256k x 36 GS881Z36T-100I bytesafe nbt pipeline/flow through tqfp 100/12 i 256k x 36 gs881z36t-80i bytesafe nbt pipeline/flow through tqfp 80/14 i 256k x 36 gs881z36t-66i bytesafe nbt pipeline/flow through tqfp 66/18 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs8 8 2 z36 t -100it. 2. the speed column indicates the cycle frequency (m h z) of the device in pipeline mode and the latency (ns) in flow through mode. each device is pipeline/flow through mode - selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only s ome of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings
rev: 1.10 8/2000 34/34 ? 1998, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com preliminary . gs 881z 18/36 t -1 1 / 100/80/66 ds/daterev. code: old; new types of changes format or content page /revisions/reason gs 881z 18/36 t rev1.04h 5/ 1999; 1.05 9/1999 format/typos ? last page/fixed ?gsgs..? in ordering information note.document/changed format of all e?s from en to en. ? timing diagrams/changed format. ex. a0 to a0. ? flow through timing diagrams/upper case ?t? in flow through. thru to through. ? pin outs/block diagrams -updated format to small caps. ? added rev history. content ? 5/fixed tqfp pin description table to match pinout/ enhancement. ? 5/changed chip enables to match pins./clarification ? ordered address inputs in pin description table to match pin out. ? changed dimension d in dimension table from 20.1 to 22.1/ correction. ? speed bins on page 1/last column-changed 12ns to 15ns and 15ns to 12ns. gs 881z 18/36 t 1.05 9/ 1999 k/ 1.06 10/1999 format ? improved appearance of timing diagrams. ? minor formatting changes. gs 881z 18/36 t 1.06 9/ 1999 k 1.07 1 /2000 l content ? new gsi logo. rev.1.08; 881z18_r1_09 content/format ? removed 166 and 150 mhz speed bins ? used 100 mhz pipeline numbers for 133 mhz ? changed all 133 mhz references to 11 ns ? updated format to comply with technical publications standards 881z18_r1_09; 881z18_r1_10 content ? updated capitance table?removed input row and changed output row to i/o

▲Up To Search▲

Price & Availability of GS881Z36T-100I

	To Download GS881Z36T-100I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .